Dissertation Defense: Design of Low-Capacitance Electrostatic Discharge (ESD) Protection Devices in Advanced Silicon Technologies
June 21, 2018 @ 10:00 AM - 12:00 PM
Announcing the Final Examination of Aihua Dong for the degree of Doctor of Philosophy
Electrostatic discharge (ESD) is defined as the transfer of charge between objects at different potentials in a quite short time. Damages introduced by ESD events results in a loss of millions dollars to the semiconductor industry each year. ESD related failure is a major IC reliability concern and this is particularly true as microelectronics technology continues shrink to nano-metric dimensions.
ESD design window research shows that ESD robustness of victim devices keep decreasing with technology scale. From 350nm bulk technology to 7nm FinFET technologies, ESD failure current (It2), ESD triggering voltage (Vt1) and gate break down voltage (Vgox) of victim Field Effect Transistors (FET) decrease a lot. In the meantime, parasitic capacitance of ESD diode with same It2 in FinFET technologies is ~3X compared with that in planar technologies. Thus transition from planar to FinFET technology requires more robust ESD protection however the large parasitic capacitance of ESD protection cell is problematic in high-speed interface design.
To reduce the parasitic capacitance, a Dual Diode Silicon Controlled Rectifier (DDSCR) is presented in this dissertation. This design can exhibit high It2, small on-state resistance (Ron), low overshoot voltage and low parasitic capacitance characteristics. Besides, different bounding materials lead to performance variations are compared.
Millimeter wave technology is also demanded low capacitance ESD design. To address this consideration, a π filter like ESD network is presented, providing robust protection for 10-60 GHz RF circuit. Like a low pass π filter, it can reflect high frequency RF signals and transmit low frequency ESD pulses. Given proper inductor value, networks can work as robust ESD solutions at a certain Giga Hertz frequency range, making this design suitable for narrow band protection in millimeter wave I/Os.
To increase the holding voltage and reduce snapback, a resistor assist triggering heterogeneous stacking structure is discussed in this dissertation as a latch-up free design, which can increase the holding voltage and also keep the trigger voltage nearly as same as a single SCR device.
Committee in Charge: Kalpathy Sundaram (Chair), Xun Gong, Lei Wei, Deliang Fan, Javier Salcedo